Description
A B PARALLEL DATA INPUTS C QH SERIAL DATA OUTPUTS
SERIAL SHIFT/ PARALLEL LOAD CLOCK F G PIN 16 = VCC PIN 8 = GND H QH GND VCC CLOCK INHIBIT SA QH
CLOCK 2 15 CLOCK INHIBIT Inputs Clock Inhibit Clock
Internal Stages SA AH a…h QB b QAn No Change No Change Output QH h QGn Operation Asynchronous Parallel Load Serial Shift via Clock Serial Shift via Clock Inhibit Inhibited Clock No Clock
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